This invention relates to digital systems, such as dynamic random access memories (xe2x80x9cDRAMsxe2x80x9d), and, more particularly to an accelerator system and method for more quickly coupling digital signals though capacitive signal lines.
The speed at which digital signals can be coupled between two nodes of a signal line is a function of the capacitance and resistance of the signal line and the distance between the two nodes. Digital signals can be coupled through signal lines that have a high resistance and a high capacitance relatively slowly, and therefore may incur a significant signal propagation delay particularly if the propagation path is long.
These signal propagation delays can be particularly troublesome in memory devices. On the one hand, it is important for memory bandwidth that signals be coupled with as little propagation delay as possible. On the other hand, it is important that memory devices be as compact as possible so that a large number can be produced on each wafer. Making memory devices compact not only minimizes the cost of the memory devices, but it also reduces propagation delays by keeping the distance between nodes be as short as possible. Yet a compact design can be achieved only by making conductors as thin as possible, thus making their resistance relatively high, and placing the conductors as close as possible to other conductors and circuit components, thus making their capacitance relatively high. For these reasons, there is a practical limit to the degree to which signal propagation delays can be reduced.
One application in which signal propagation delay is particularly problematic is coupling data signals through input/output (xe2x80x9cI/Oxe2x80x9d) or read/write (xe2x80x9cR/Wxe2x80x9d) lines extending though memory banks in a DRAM. With reference to FIG. 1, several memory banks 100, in this example, eight memory banks 100(1)-100(8), are fabricated on a semiconductor substrate 104. Each of the memory banks 100 includes two rows of memory cell arrays 108, 110 which, in this example, each contain 32 memory cell arrays 108(1)-108(32) and 110(1)-110(32). The memory cells (not shown) in each array 108, 110 are selectively coupled to column circuits 114 adjacent each of the arrays 108, 110. Each of the column circuits 114 includes a sense amplifier 116 for each column in the memory array and a column decoder 118. The sense amplifier 116 determines the voltage to which a memory cell that is coupled to the sense amplifier 116 is charged and outputs a corresponding data bit. The column decoder 118 decodes a column address and selects one of the sense amplifiers corresponding to the decoded column address. A data bit is then coupled from the selected sense amplifiers 116 in each array 108, 110 to a respective I/O line 120. Therefore, since there are 32 arrays 108, 110 in each of two rows, there are a total of 64 I/O lines 120, and each memory read access produces 64 bits of read data.
The column decoders 118 and I/O lines 120 are also used for write accesses. In a write access, 64 bits of write data are coupled through the I/O lines 120, and the column decoders 120 couple one bit of write data to a column of memory cells in each of the arrays 108, 120. The I/O lines 120 are therefore bi-directional since they are used to couple read data from the arrays 108, 110 and write data to the arrays 108, 110.
The rate at which memory read and write accesses can occur depends, at least in part, on the rate at which data bits can be coupled through the I/O lines 120. For a memory write, the 64 write data bits are coupled to the I/O lines 120 at substantially the same time. However, the memory write cannot be completed until a write data bit has been coupled all of the way to the farthest arrays 108(1), 110(1). Similarly, in a memory read, the 64 read data bits are coupled from the column decoders 118 to the I/O lines 120 at substantially the same time. But the read data cannot be coupled to other circuits until a read data bit has been coupled from the farthest arrays 108(1), 110(1). The increasing capacity of memory arrays 108, 110 and the increasing number of arrays 108, 110 in each bank, which is required to increase the storage capacity of memory devices, results in ever longer I/O lines 120. These longer I/O lines threaten to limit the memory bandwidth of memory devices.
The manner in which a digital signal is delayed as it is coupled through a capacitive signal line will be apparent from the graph shown in FIG. 2 in which time is plotted along the horizontal axis and signal level is plotted along the vertical axis. At time T0, one node of the signal line quickly transitions from low to high to produce the signal 130. However, because of the capacitance and resistance of the signal line, the line must be charged by the signal 130. As a result, the signal 130 produces a signal 134 at a distant node that increases much more slowly than the signal 130. If a circuit (not shown) coupled to the distant node detects a level transition at a transition voltage level VTRANS, the circuit will not detect the transition of the signal 130 until T1. Thus, the signal 130 is propagated between the two nodes with a propagation delay of T1. As mentioned above, such delays can be problematic in memory devices, such as in coupling signals through the I/O lines 120.
In the past, various attempts have been made to increase the speed at which digital signals are coupled through signal lines other than by altering the electrical properties of the signal lines. For example, one or more repeaters, such as inverters, have been coupled in series with the signal line to reduce the delay in detecting a signal transition. The manner in which an inverter can reduce propagation delays can be seen from the graph of FIG. 3. At time T0, one node of the signal line again quickly transitions from low to high to produce the signal 130. Again, the signal 130 must charge the line because of its capacitance. However, two inverters (not shown) are coupled to the signal line at first and second nodes that are one-third and two-thirds, respectively, the distance to a node where the signal 134 was produced in the example of FIG. 2. A signal 140 at the first node where the first inverter was located, a signal 144 at the second node where the second inverter was located, and a signal 148 at the node where the signal was produced in FIG. 2 are shown in FIG. 3 (this example ignores the inverting nature of the signal for purposes of clarity). Although the signals 140, 144 still initially increase relatively slowly, as soon as they reaches the threshold of the respective inverter they quickly transitions from low-to-high. As a result, the signal 148 increases faster than the signal 130 shown in FIG. 2, and it therefore reaches the transition voltage level VTRANS at time T2, which is an earlier time than the time T1, that the signal 134 reached the voltage level VTRANS.
Although inverters can reduce signal line propagation delays, the use of inverters can create other problems. For example, inverters convert what would otherwise be bi-directional signal lines to unidirectional signal lines so that twice as many signal lines are required to couple signals in two directions. The use of inverters, for example, would require that the 64 I/O lines 120 used in each memory bank 100 in the example of FIG. 1 be increased to 128 I/O lines 120. However, doing so would only serve to make the memory banks 100 less compact and/or the signal lines even closer together, thereby tending to increase signal propagation delays.
Another approach to reducing signal propagation delay in I/O lines 120 is to bias or equilibrate the lines at the midpoint of the voltages of the signals coupled through the lines. For example, the I/O lines 120 can be equilibrated to VCC/2, where the signals coupled through the signals lines will transition between VCC and zero volts. Equilibrating the I/O lines to VCC/2 reduces signal propagation delay because the voltage in each signal line must transition only half of the voltage between zero volts and VCC. In contrast, in the example shown in FIG. 2, the voltage in the signal line must transition between almost 100% of the two voltage levels of the signal coupled through the line. While biasing the I/O lines 120 to VCC/2 can reduce signal propagation delay, it requires additional circuitry and complexity, and it only marginally reduces signal propagation delay.
Still another approach to reducing signal propagation delays is to couple xe2x80x9caccelerator circuitsxe2x80x9d to the signal lines at spaced apart locations. Accelerator circuits are circuits that have both an input and an output coupled to the signal lines so that the signal lines remain bi-directional. Accelerator circuits therefore do not have the disadvantage of inverters, which require doubling the number of signal lines to couple signals in both directions. Examples of accelerator circuits are shown and described in an article by Dobbelaere et al. entitled xe2x80x9cRegenerative Feedback Repeaters for Programmable Interconnectionsxe2x80x9d, IEEE Journal of Solid-State Circuits, Vol. 30, No. 11, November 1995, and in an article by Wu et al., entitled xe2x80x9cDelay Models and Speed Improvement Techniques for RC Tree Interconnections Among Small-Geometry CMOS Invertersxe2x80x9d, IEEE Journal of Solid State Circuits, Vol. 25, No. 5, October 1990. Although conventional accelerator circuit can reduce signal propagation delays without producing the disadvantages of inverter, they nevertheless still require a significant delay period before they can react to a signal translation at a distant node because of the time required to drive the signal line to the transition voltage level VTRANS of the accelerator circuit.
Although the problem of signal propagation delays in memory device signal lines had been primarily explained with reference to the I/O lines 120 shown in FIG. 1, the problem is not limited to signal propagation delays in these lines. For example, address lines are generally numerous and fairly long so propagation delays in these lines also adversely affect the performance of memory devices. Other examples will be apparent to one skilled in the art. Digital signal propagation delays are also a problem in digital system other than memory devices.
There is therefore a need for an accelerator circuit and method that can be more effective than conventional accelerators in reducing signal propagation delays, particularly in memory devices and particularly in relatively long signal lines like I/O lines and address lines.
A system and method of accelerating the coupling of digital signals through respective signal lines precharges each of the signal lines. Alternating signal lines are preferably precharged to respective high and low voltages so that each signal line precharged to a high voltage is adjacent signal lines that have been precharged to a low voltage, and vice-versa. After the signal lines have been precharged, the system and method detects whether the voltage of the signal line has changed from the precharged voltage. In response to detecting that the voltage of the signal line has changed, the system and method drives the signal line toward a voltage that increases the voltage change. Where alternating signal lines are precharged to respective high and low voltages, the signal lines precharged to a low voltage are driven to a high voltage and the signal lines precharge to a high voltage are driven to a low voltage. As a result, any coupling from one signal line to an adjacent signal line tends to change the voltage of the signal line in a manner opposite the detected change. The system and method is particularly useful for accelerating the coupling of digital signals in memory devices, such as read data and write data signals coupled through I/O lines in a memory array.